Self-Anchored Catalyst Interface Enables Ordered Via Array Formation from Submicrometer to Millimeter Scale for Polycrystalline and Single-Crystalline Silicon.

Defying text definitions of wet etching, metal-assisted chemical etching (MacEtch), a solution-based, damage-free semiconductor etching method, is directional, where the metal catalyst film sinks with the semiconductor etching front, producing 3D semiconductor structures that are complementary to the metal catalyst film pattern. The same recipe that works perfectly to produce ordered array of nanostructures for single-crystalline Si (c-Si) fails completely when applied to polycrystalline Si (poly-Si) with the same doping type and level. Another long-standing challenge for MacEtch is the difficulty of uniformly etching across feature sizes larger than a few micrometers because of the nature of lateral etching. The issue of interface control between the catalyst and the semiconductor in both lateral and vertical directions over time and over distance needs to be systematically addressed. Here, we present a self-anchored catalyst (SAC) MacEtch method, where a nanoporous catalyst film is used to produce nanowires through the pinholes, which in turn physically anchor the catalyst film from detouring as it descends. The systematic vertical etch rate study as a function of porous catalyst diameter from 200 to 900 nm shows that the SAC-MacEtch not only confines the etching direction but also enhances the etch rate due to the increased liquid access path, significantly delaying the onset of the mass-transport-limited critical diameter compared to nonporous catalyst c-Si counterpart. With this enhanced mass transport approach, vias on multistacks of poly-Si/SiO2 are also formed with excellent vertical registry through the polystack, even though they are separated by SiO2 which is readily removed by HF alone with no anisotropy. In addition, 320 μm square through-Si-via (TSV) arrays in 550 μm thick c-Si are realized. The ability of SAC-MacEtch to etch through poly/oxide/poly stack as well as more than half millimeter thick silicon with excellent site specificity for a wide range of feature sizes has significant implications for 2.5D/3D photonic and electronic device applications.